(Rapidus US)Standard Cell / GPIO Design Engineer (2 nm Technology Node)
- 職務内容
- We are seeking skilled engineers to join our Foundation IP Design Team, focusing on Standard Cell and GPIO (General Purpose I/O) development.
Engineers with expertise in circuit design, layout, reliability, or DTCO are all welcome.
This position involves close collaboration with process, device, and enablement teams to deliver high-quality, high-performance IP that supports leading-edge logic technologies.
Key Responsibilities:
₋Design and optimize standard cells and GPIO circuits (input/output buffers, level shifters, ESD structures, and special cells) for advanced technology nodes.
-Perform transistor-level circuit design and HSPICE simulations for performance, leakage, and robustness verification across PVT corners.
-Collaborate with layout engineers to ensure design rule compliance, area efficiency, and manufacturability.
-Work with process integration and DTCO teams to co-optimize transistor architectures, layout patterns, and reliability structures.
-Support characterization and model generation for timing, power, and noise modeling.
-Participate in ESD and latch-up design verification, ensuring compliance with foundry reliability standards.
-Analyze silicon test results and feedback for model correlation and IP quality improvement.
-Cooperate with EDA vendors and PDK teams to validate design enablement and sign-off flows. - 応募資格/応募条件
- Requirements:
-B.S. or M.S. in Electrical Engineering, Electronics, or Microelectronics.
-3+ years of experience in standard cell, I/O, or custom circuit design for advanced CMOS nodes (≤ 5 nm preferred).
-Strong understanding of CMOS device behavior, low-power design techniques, and circuit optimization.
-Hands-on experience with EDA tools for schematic design, simulation, and layout verification (e.g., Cadence Virtuoso, HSPICE, Calibre).
-Familiarity with DRC/LVS/EMIR verification flows and reliability checks.
-Strong problem-solving, analytical, and cross-functional collaboration skills.
-Effective communication and documentation skills in English.
Preferred Qualifications :
-Experience with nanosheet / GAA transistor architectures or FinFET-based IP design.
-Familiarity with DTCO and library automation / QA flows (Python, TCL, etc.).
-Experience with test-chip development or IP qualification (Level-1 / Level-2).
-Knowledge of characterization tools (Liberate, SiliconSmart) and Liberty model validation.
-Understanding of ESD protection, latch-up prevention, and pad ring integration.
-Japanese language proficiency is a plus. - 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany (NY), Santa Clara (CA), or Tokyo (Japan)
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1STEP 1 Web Entry
Please apply via the entry form.
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STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
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STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
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STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
