(Rapidus US)SRAM Development Engineer
- 職務内容
- We are seeking talented engineers to join our SRAM Development Team, responsible for SRAM bitcell, peripheral circuit, macro, and compiler development, as well as SRAM technology roadmap planning and DTCO (Device-Technology Co-Optimization).
This role offers the opportunity to work on cutting-edge memory architectures while collaborating closely with process, device, DTCO, and design enablement teams to define scalable SRAM solutions for future technology nodes.
Key Responsibilities:
-Design and develop SRAM bitcells, peripheral circuits, SRAM macros, and compilers for advanced technology nodes (2 nm and beyond).
-Perform transistor-level circuit design and simulation to meet performance, power, stability, and variability requirements.
-Collaborate with process integration and device teams to improve SRAM cell robustness, yield, and manufacturability through DTCO activities.
-Define and maintain the SRAM technology roadmap, including scaling strategy, bitcell architecture evolution, and feature planning for future nodes.
-Lead and contribute to DTCO studies for SRAM, evaluating device options, layout constructs, Vt choices, and PPA trade-offs.
-Work closely with standard cell, GPIO, and logic IP teams to ensure cross-IP alignment and consistent design assumptions.
-Participate in SRAM macro architecture definition and compiler feature planning (timing, redundancy, power management).
-Conduct layout verification, DRC/LVS debug, parasitic extraction, and variation analysis for SRAM arrays and peripherals.
-Analyze silicon test and characterization data and support failure analysis and yield improvement activities.
-Work with EDA vendors and PDK teams to define and validate SRAM modeling, sign-off, and enablement flows.
-Contribute to SRAM qualification test chips and shuttle programs. - 応募資格/応募条件
- Required Qualifications :
-B.S. or M.S. in Electrical Engineering, Electronics, or related field.
-3+ years of experience in SRAM circuit design, memory architecture, or advanced CMOS memory development.
-Strong knowledge of SRAM bitcell design, peripheral circuits, and variability-aware design techniques.
-Experience with EDA tools for schematic design, layout, and simulation (e.g., Cadence Virtuoso, Synopsys HSPICE, Siemens Calibre).
-Solid understanding of device physics, PVT variation, and reliability challenges at advanced nodes.
-Ability to work effectively with cross-functional teams (process, DTCO, EDA, test, and enablement).
-Strong communication and technical documentation skills in English.
Preferred Qualifications :
-Experience with FinFET or nanosheet (GAA) SRAM design.
-Experience contributing to SRAM technology roadmap definition or long-term memory scaling strategy.
-Familiarity with DTCO methodologies, including device/layout co-optimization and trade-off analysis.
-Experience with SRAM compiler development and automation flows.
-Hands-on experience with silicon debug, failure analysis, and test-chip bring-up.
-Knowledge of EDA PDK development or SRAM model validation flows.
-Business-level Japanese proficiency is a plus. - 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1STEP 1 Web Entry
Please apply via the entry form.
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STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
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STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
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STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
