(Rapidus US)Senior Chiplet Package Design Engineer (2.5D / 3D Integration)
- 職務内容
- We are seeking a highly motivated Chiplet Package Design Engineer to drive the development of advanced packaging solutions for next-generation semiconductor products. This role focuses on 2.5D and 3D heterogeneous integration, enabling high-performance computing, AI, networking, and advanced SoC platforms.
The candidate will work cross-functionally with silicon design, system architecture, manufacturing, and OSAT partners to deliver cutting-edge chiplet-based packaging solutions.
Key Responsibilities
-Lead the design and development of 2.5D/3D package architectures (e.g., interposer-based, fan-out, and 3D stacking)
-Define and optimize chiplet integration strategies, including die partitioning, interface definition, and interconnect topologies
-Develop package layout and routing for high-speed/high-density interconnects (e.g., HBM, UCIe, PCIe, SerDes)
-Perform and guide signal integrity (SI), power integrity (PI), and thermal analysis
-Collaborate with silicon teams on bump/pad design, floorplanning, and co-design methodologies
-Drive package-substrate co-design including material selection and stack-up definition
-Interface with OSATs and foundries for manufacturability, yield improvement, and cost optimization
-Support DFx (DFM, DFT, DFA) and reliability validation (warpage, stress, electromigration)
-Contribute to package technology roadmap for advanced nodes (2nm and beyond)
-Participate in bring-up, validation, and failure analysis of packaged devices
What We Offer :
-Opportunity to work on cutting-edge chiplet and heterogeneous integration technologies
-Collaboration with global teams across the US and Japan
-Exposure to next-generation nodes (2nm and beyond)
-Competitive compensation and career growth opportunities - 応募資格/応募条件
- Required Qualifications :
-B.S. or M.S. in Electrical Engineering, Mechanical Engineering, Materials Science, or related field
-5+ years of experience in semiconductor package design, especially advanced packaging
-Hands-on experience with 2.5D/3D packaging technologies (e.g., silicon interposer, TSV, hybrid bonding)
-Strong knowledge of high-speed interfaces and package-level SI/PI considerations
-Experience with industry-standard tools (e.g., Cadence Allegro Package Designer, Sigrity, Ansys HFSS, RedHawk-SC Electrothermal)
-Understanding of package manufacturing processes and OSAT ecosystem
-Ability to work in cross-functional and global teams
Preferred Qualifications :
-Experience with chiplet architectures and standards (e.g., UCIe)
-Knowledge of HBM integration, AI accelerators, or HPC systems
-Experience with thermal/mechanical simulation tools (e.g., Ansys Mechanical, Icepak)
-Familiarity with advanced substrates (ABF, glass core, fan-out RDL)
-Experience in co-design with silicon (die-package-system co-optimization)
-Knowledge of yield analysis and reliability modeling
-Japanese language skills (for collaboration with Japan-based teams)
- 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany, NY (USA) / Santa Clara, CA (USA) / Tokyo (Japan) / Chitose (Japan)
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1STEP 1 Web Entry
Please apply via the entry form.
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STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
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STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
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STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
