(Rapidus US)Macro Analog Design Engineer
- 職務内容
- This position focuses on macro and custom layout design for evaluation macros, memory, logic, and analog/mixed-signal functional blocks in advanced semiconductor process and device development.
Through layout optimization considering PPA (Performance, Power, Area), reliability, manufacturability (DFM), and yield, the engineer contributes to the validation and advancement of process and device technologies.
The engineer will work closely with circuit designers, process/device teams, and PDK teams, and will play a key role throughout the development phases from early design through volume ramp.
Key Responsibilities:
Macro Layout (Primary Responsibility)
-Macro/custom layout design for memory, logic, and analog/mixed-signal functional blocks
-Layout variation design intended for device characterization and process validation
-Layout optimization considering DRC/LVS/DFM/DFY, EMIR, and reliability
-Layout design and revision control for test chips (TEGs) and evaluation macros
-Support correlation analysis between silicon results (electrical characteristics, reliability, yield) and layout conditions
Cross-Functional Collaboration
-Collaborate with circuit designers to define layout constraints reflecting circuit intent
-Work with process and device development teams to define evaluation conditions and viewpoints
-Provide feedback to PDKs, including design rules and layout guidelines
Stretched Goals Include:
-Contribute to circuit design for memory, logic, or analog blocks
-Perform circuit simulation and variability analysis using SPICE or equivalent tools
-Take ownership of post-layout circuit verification
-Propose optimization by integrating circuit conditions and physical implementation conditions
-Lead development of evaluation macros spanning both circuit and layout domains
- 応募資格/応募条件
- Required Qualifications:
-Bachelor’s degree or higher in Semiconductor Engineering, Electrical Engineering, Physics, or a related field
-3+ years of hands-on experience in macro/custom layout design
-Experience with DRC/LVS-based verification flows
-Fundamental knowledge of advanced process design rules and manufacturing constraints
-Basic understanding of circuit operation
Preferred Qualifications:
-Experience with advanced technology nodes (7nm or below, FinFET/GAA, etc.)
-Experience in memory or analog/mixed-signal circuit design
-Cross-functional experience with process and/or device development teams
-Ability to communicate technical topics effectively in English
Desired Attributes:
-Strong technical curiosity and proactive approach to problem solving
-Ability to collaborate effectively with cross-functional teams
-Flexibility to work in fast-paced and uncertain advanced R&D environments
- 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany, NY
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1STEP 1 Web Entry
Please apply via the entry form.
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STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
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STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
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STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
