(Rapidus US)DFT Engineer
- 職務内容
- - Define and implement DFT architectures for technology development test chips, focusing on scan, boundary scan, and memory BIST.
- Function and timing verification of implemented DFT circuit, evaluate test coverage with DFT simulation (ATPG, BIST, Fault simuation).
- Propose the best test solution with analysis among test coverage, test cost, test time
- Collaborate with design teams to integrate DFT features from RTL through physical implementation.
- Develop and validate ATPG and MBIST patterns; support test bring-up and debug on silicon.
- Analyze test data from silicon to identify systematic issues and improve process yield.
- Engage with EDA vendors to evaluate and improve DFT tools and methodologies for advanced nodes.
- Document best practices and contribute to the enablement of scalable DFT flows across future technology nodes.
- Support cross-functional teams spanning design, process, product engineering, and reliability. - 応募資格/応募条件
- - Education: Bachelor's or Master's in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 3+ years (Master's) or 5+ years (Bachelor's) in digital IC design, standard cell library development, or design enablement.
- Understanding of digital design flow from architecture to physical implementation and synthesis.
- Proficiency in Verilog and/or SystemVerilog RTL coding.
- Experience with standard ASIC design tools (synthesis, simulation, STA, formal verification).
- Familiarity with design rules, process variations, and reliability for advanced nodes (preferably 5nm and below).
- Strong analytical and problem-solving skills.
Proficiency in scripting languages (e.g., Python, Perl, TCL, C/C++) for design flow automation.
- Excellent communication and interpersonal skills for global teamwork.
Preferred Skills and Qualifications
- Advanced Degree: Master’s or PhD in Electrical Engineering or related STEM field is desirable.
- DTCO Experience: Hands-on experience with DTCO, collaborating with process and device teams to optimize PPA.
- Foundry Experience: Experience working with external foundries or managing IP vendor relationships is a plus.
- EDA Tools: Direct experience using specific EDA tools from Synopsys, Cadence, or Siemens Calibre (e.g., Fusion Compiler, Innovus, Calibre).
- Industry Knowledge: Understanding of emerging technologies relevant to sub-2nm nodes. - 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany, NY
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
-
以下はモデルケースですので、面接回数など若干変更する場合もあります。
-
STEP 1STEP 1 Web Entry
Please apply via the entry form.
-
STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
-
STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
-
STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
-
- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
