(Rapidus US)DFT design / methodology development Engineer
- 職務内容
- You will be responsible for the Design for Test (DFT) strategy within the 2nm reference flow. This role involves integrating advanced
Scan and MBIST tools to ensure high testability for complex GAA designs. You will also lead the evaluation and adoption of
next-generation DFT methodologies to address the challenges of ultra-fine process nodes.
You will play a central leadership role in building the world’s most advanced 2nm and next‑generation enablement ecosystem,
shaping the foundation for future semiconductor innovation.
You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)
Key Responsibilities:
-Integrate Scan and MBIST (Memory Built-In Self-Test) tools into the digital reference flow.
-Evaluate and implement advanced DFT technologies, such as Streaming Scan Network (SSN), to optimize test data volume and test time.
-Develop and validate ATPG (Automatic Test Pattern Generation) methodologies utilizing cell-aware (intra-cell) fault models to achieve high defect coverage at the 2nm node.
-Conduct evaluation and feasibility studies for new failure analysis methodologies to improve yield ramp-up.
-Work closely with EDA vendors to implement these advanced DFT features and collaborate with design partners for pattern generation and silicon-based failure diagnosis.
-Support DFT implementation and pattern execution for internal Rapidus test chips.
-Provide customers with comprehensive DFT guidelines and technical support. - 応募資格/応募条件
- Qualifications:
-Solid understanding of DFT methodologies (Scan, MBIST, ATPG).
-Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.
-Familiarity with advanced DFT architectures (e.g., SSN, packetized test) and cell-aware testing is highly desirable.
-Proven ability to collaborate with external stakeholders, including EDA vendors and design service partners.
-Collaboration: Proven ability to work effectively with external stakeholders, including EDA vendors and design service partners.
-Education: BS/MS/PhD in Electrical Engineering or a related technical field.
-Language: Professional proficiency in English (Japanese skills are a plus). - 雇用形態
- Probational period: 3 months (conditions of the employment remains the same)
- 給与
- The exact salary will be determined based on qualifications, experience and location.
- 昇給
- Potential for career growth based on performance and company needs.
- 勤務地
- Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)
- 勤務時間
- Flex time: 40 hours weekly with start and end times between 9 am and 5:30 pm. 1 hour lunch break.
- 休日休暇
- We observe these paid holidays: New Year’s Day, Memorial Day, Independence Day, Labor Day, Thanksgiving, the day after Thanksgiving, and Christmas. We observe founding anniversary (8/10) and employees may take personal holidays of their choice (up to 4 days, depends on the start date).
Paid Sick Leave based on NYS law
PTO: front loaded, max 20 days/year - 加入保険
- Medical, Dental, Vision, 401(k) benefits are provided.
- 待遇・手当
- n/a
- 各種制度
- We offer comprehensive on-the-job training to ensure your success.
- 応募書類
- Applicants must submit a current resume to be considered for this position.
- その他
- We are a smoke-free workplace in accordance with company policy and local regulations.
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1STEP 1 Web Entry
Please apply via the entry form.
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STEP 2STEP 2 Document Screening
We will review your application based on the information provided.
Regardless of the result, we will notify you of the outcome. -
STEP 3STEP 3 First Interview
Conducted online.
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STEP 4STEP 4 Final Interview
Conducted online. There will be confirmation items.
Depending on the position, the number of interviews may not be limited to two.
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STEP 5STEP 5 Job Offer
Your application will be kept strictly confidential.
The information provided will only be used for the purpose of the selection process.
It generally takes about 2–3 weeks from document screening to job offer.
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
採用担当
