{"id":1511,"date":"2026-04-11T15:10:00","date_gmt":"2026-04-11T06:10:00","guid":{"rendered":"https:\/\/www.rapidus.inc\/?post_type=news_topics&#038;p=1511"},"modified":"2026-04-30T21:12:47","modified_gmt":"2026-04-30T12:12:47","slug":"nedo-approves-rapidus-fy2026-plan-and-budget-for-2nm-semiconductor-projects","status":"publish","type":"news_topics","link":"https:\/\/www.rapidus.inc\/en\/news_topics\/information\/nedo-approves-rapidus-fy2026-plan-and-budget-for-2nm-semiconductor-projects\/","title":{"rendered":"NEDO Approves Rapidus\u2019 FY2026 Plan and Budget for 2nm Semiconductor Projects Approval covers \u201cResearch and Development of 2nm-Generation Semiconductor Integration Technologies and Short TAT Manufacturing Technology Based on Japan\u2013U.S. Collaboration\u201d and \u201cDevelopment of Chiplet, Package Design and Manufacturing Technology for 2nm-Generation Semiconductors\u201d"},"content":{"rendered":"\n<p>TOKYO, April 11, 2026 \u2013 <a href=\"https:\/\/www.rapidus.inc\/en\/\" target=\"_blank\" rel=\"noreferrer noopener\">Rapidus Corporation<\/a> today announced that its plans and budget for fiscal year 2026 have been approved by Japan\u2018s New Energy and Industrial Technology Development Organization (NEDO). The approval covers two commissioned projects under NEDO\u2019s \u201cPost-5G Information and Communication Systems Infrastructure Enhancement R&amp;D Project \/ Development of Advanced Semiconductor Manufacturing Technology (Commissioned).&#8221; These projects are the \u201cResearch and Development of 2nm-Generation Semiconductor Integration Technology and Short Turnaround Time (TAT) Manufacturing Technology Based on Japan\u2013U.S. Collaboration\u201d and \u201cDevelopment of Chiplet, Package Design and Manufacturing Technology for 2nm-Generation Semiconductors.\u201d<\/p>\n\n\n\n<p>The first of these projects, focused on front-end processes, was launched in November 2022 as part of Japan\u2019s next-generation semiconductor R&amp;D effort. Under this program, in fiscal year 2025, Rapidus began its pilot line in April using manufacturing equipment installed at its Innovative Integration for Manufacturing (IIM-1) foundry in Chitose, Hokkaido. The company proceeded with prototype development, starting with the verification of 2nm gate-all-around (GAA) transistor operation on 300mm wafers. Followed by a pre-release process design kit (PDK) to early-adopter customers and establishing an environment that enables prototyping, Rapidus achieved its fiscal year front-end process goals.<\/p>\n\n\n\n<p>The second project, targeted at back-end processes, was launched in March 2024. In fiscal year 2025, at Rapidus Chiplet Solutions (RCS)\u2014a research and development facility for semiconductor back-end processes at the Chitose plant of Seiko Epson Corporation\u2014Rapidus began installing manufacturing equipment in April 2025 and constructed a pilot line to establish mass production technology. Furthermore, it prototyped an organic insulating film redistribution layer (RDL) interposer using a 600mm square panel\u2014an industry first\u2014and continued to develop a reference flow compatible with 3D packaging technology and the latest back-end processes.<br>&nbsp;<br>With the approval of this year&#8217;s plan and budget, Rapidus will proceed with the development of mass production technologies for next-generation 2nm logic semiconductors. The company will generally release its PDK required for customers\u2019 semiconductor designs and implement and validate the equipment, transport systems and production management solutions necessary for the short-TAT production system it has developed on its pilot line.<br>&nbsp;<br>Relative to the back-end processes, Rapidus will begin full-scale operation of the RCS pilot line, conduct verification of 2.xD and 3D package manufacturing processes and develop design and testing technologies for high-efficiency, high-performance chiplet packages optimized for each application.<\/p>\n\n\n\n<p>\u201cIn fiscal year 2025, Rapidus made steady progress on its projects, including the successful verification of Japan\u2019s first 2nm GAA transistor and the industry\u2019s first prototype of an organic insulating film RDL interposer using a 600mm square panel. We would like to take this opportunity to express our sincere gratitude to the Ministry of Economy, Trade and Industry, NEDO, Hokkaido, Chitose City and all others for their generous cooperation,\u201d said Dr. Atsuyoshi Koike, representative director and CEO, Rapidus Corporation. \u201cWith the approval of the NEDO project plan and budget, in the wafer process, we will further improve the accuracy of prototypes and implement measures to increase yield. For the chiplet area, we will continue to advance the development of 2.xD and 3D packaging manufacturing technologies, including those for 2nm-generation semiconductors, with the aim of steadily progressing toward the start of mass production targeted for 2027.\u201d<\/p>\n\n\n\n<p><br><\/p>\n\n\n\n<p><strong>About Rapidus Corporation<\/strong>&nbsp;<\/p>\n\n\n\n<p>Rapidus Corporation aims to develop and manufacture the world&#8217;s most advanced logic semiconductors. We will create new industries together with our customers through the development and provision of services to shorten cycle times in design, wafer processes, 3D packaging and more. We will continue to challenge ourselves in order to contribute to the fulfillment, prosperity and happiness of people\u2019s lives through the use of semiconductors.<\/p>\n\n\n\n<div style=\"border:1px solid #333;padding:20px;margin-bottom:30px\">Rapidus Corporation\n<br>\n<div class=\"flexli\"><span>Headquarters: <\/span><span>4-1 Kojimachi, Chiyoda-ku, Tokyo 102-0083, Japan<\/span>\n<\/div>\n\n<div class=\"flexli\"><span>Founded: <\/span>\n<span>August 10, 2022<\/span>\n<\/div>\n\n<div class=\"flexli\"><span>Business Areas: <\/span>\n<span>Development, design, manufacture, and sale of semiconductor devices, integrated circuits and other electronic components<\/span>\n<\/div>\n\n\n<div class=\"flexli\"><span>Capital (as of February 27, 2026): <\/span>\n<span>274.95 billion yen (including legal capital surplus)\n<\/span>\n<\/div>\n<\/div>\n\n\n\n<p><\/p>\n","protected":false},"featured_media":0,"parent":0,"menu_order":0,"template":"","news_cat":[9],"class_list":["post-1511","news_topics","type-news_topics","status-publish","hentry","news_cat-information","en-US"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - 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