{"id":1240,"date":"2025-04-01T15:29:55","date_gmt":"2025-04-01T06:29:55","guid":{"rendered":"https:\/\/www.rapidus.inc\/wp\/?post_type=news_topics&p=1240"},"modified":"2025-04-01T16:21:31","modified_gmt":"2025-04-01T07:21:31","slug":"nedo-fy2025-approval","status":"publish","type":"news_topics","link":"https:\/\/www.rapidus.inc\/en\/news_topics\/information\/nedo-fy2025-approval\/","title":{"rendered":"NEDO Approves Rapidus\u2019 FY2025 Plan and Budget for 2nm Semiconductor Projects"},"content":{"rendered":"\n

Approval Covers \u201cResearch and Development of 2nm-Generation Semiconductor Integration Technologies and Short TAT Manufacturing Technology Based on Japan\u2013U.S. Collaboration\u201d and \u201cDevelopment of Chiplet, Package Design, and Manufacturing Technology for 2nm-Generation Semiconductors\u201d<\/em><\/p>\n\n\n\n

TOKYO, April 1, 2025<\/strong> \u2013 Rapidus Corporation (Head Office: 4-1 Kojimachi, Chiyoda-ku, Tokyo; Representative Director and CEO: Dr. Atsuyoshi Koike) today announced that its plans and budget for fiscal year 2025 have been approved by Japan\u2018s New Energy and Industrial Technology Development Organization (NEDO). The approval covers two commissioned projects under NEDO\u2019s \u201cPost-5G Information and Communication Systems Infrastructure Enhancement R&D Project \/ Development of Advanced Semiconductor Manufacturing Technology (Commissioned).” These projects are the \u201cResearch and Development of 2nm-Generation Semiconductor Integration Technology and short TAT (turnaround time) Manufacturing Technology Based on Japan\u2013U.S. Collaboration\u201d and \u201cDevelopment of Chiplet, Package Design and Manufacturing Technology for 2nm-Generation Semiconductors.\u201d<\/p>\n\n\n\n

The first of these projects, focused on front-end processes, was launched in November 2022 as part of Japan\u2019s next-generation semiconductor R&D effort. Under this program, Rapidus has continued construction of the Innovative Integration for Manufacturing (IIM) facility in Chitose, Hokkaido, which will serve as its production base. It also sent engineers to IBM in the U.S. to jointly develop 2nm logic semiconductor mass production technologies and continued to achieve target performance as planned. Furthermore, Rapidus has installed EUV lithography and other production equipment at the IIM facility, and started cleanroom operation. As a result of these efforts, the company achieved its performance targets for FY2024.<\/p>\n\n\n\n

The second project, focused on back-end processes, was launched in March 2024. Its objective is to enable the development of larger and more power-efficient chiplet packages that use 2nm-generation semiconductors. To support this goal, the project is establishing the design kits and chiplet testing technologies needed for mass production and package design.<\/p>\n\n\n\n

Rapidus is advancing this initiative in international collaboration with IBM (U.S.), Fraunhofer (Germany) and A*STAR IME (Singapore). As a result of these collaborations, the determination of the basic process flow and selection of equipment were completed in FY2024. It also decided to establish a new R&D base\u2014Rapidus Chiplet Solutions (RCS)\u2014at Seiko Epson Corporation\u2019s Chitose Plant, which is adjacent to the IIM. Preparations for RCS have been underway since October 2024.<\/p>\n\n\n\n

With the approval of this year’s plan and budget, the pilot line will start up in April with the manufacturing equipment that has been installed in the front-end process area. Rapidus will develop prototype 2nm Gate-All-Around (GAA) transistors on 300mm wafers. It will also release a Process Design Kit (PDK) for early customers and prepare an environment where customers can begin prototyping.<\/p>\n\n\n\n

Relative to the back-end processes, in April Rapidus will begin installing manufacturing equipment at RCS. The site will develop a pilot line to establish mass production techniques. Rapidus will also work on:<\/p>\n\n\n\n