{"id":1165,"date":"2024-12-11T10:00:51","date_gmt":"2024-12-11T01:00:51","guid":{"rendered":"https:\/\/www.rapidus.inc\/wp\/?post_type=news_topics&p=1165"},"modified":"2024-12-10T21:16:22","modified_gmt":"2024-12-10T12:16:22","slug":"rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2","status":"publish","type":"news_topics","link":"https:\/\/www.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2\/","title":{"rendered":"Rapidus Collaborates with Synopsys to Shorten Semiconductor Design Cycles"},"content":{"rendered":"\n

TOYKO, SEMICON Japan Booth #2148, Dec. 10, 2024<\/strong> \u2013 Rapidus Corporation<\/a>, a manufacturer of advanced logic semiconductors, today announced that it has signed an agreement with Synopsys Inc<\/a>., a leading provider of silicon to systems design solutions, to enable a solution that will shorten design cycle time, using a revolutionary new approach to natively model process sensitivity and variation in the design steps. This new approach dramatically reduces the need for expensive re-characterization of libraries and memories during different phases of the process evolution leading to a significant reduction in design iterations and acceleration of the overall project execution cycle.<\/p>\n\n\n\n

As part of the agreement, Synopsys will develop advanced design flows leveraging its AI-driven EDA suite and enable a broad IP portfolio on Rapidus\u2019 2nm gate-all-around (GAA) process. The collaboration will facilitate Rapidus\u2019 Design for Manufacturing and Co-Optimization (DMCO) concept for simultaneously optimizing design and manufacturing and enabling agile design.<\/p>\n\n\n\n

Characterization of the IP library is one of the bottlenecks in semiconductor design cycle time because the IP needs to be recharacterized each time the process design kit (PDK) or manufacturing process is updated. It can take two to three months to generate a timing model, which drastically slows down the design process. The new DMCO solution will address these bottlenecks by using Synopsys AI-driven EDA products, including Synopsys PrimeShieldTM<\/sup>, a machine learning (ML)-based timing model generation tool employing sensitivity libraries whenever PDKs or manufacturing processes are updated. Additionally, calibration using silicon data from Rapidus\u2019 short turnaround time (TAT) manufacturing process will improve model accuracy and accelerate design convergence.<\/p>\n\n\n\n

\u201cSynopsys continues to play a mission-critical role as an on-ramp to the world\u2019s leading foundries and we are often the first stop for foundry enablement,\u201d said Sassine Ghazi, president and CEO of Synopsys. \u201cOur extensive collaboration with Rapidus across Synopsys AI-driven EDA flows, IP and expert methodology services will facilitate an advanced DMCO solution that will enable designers to achieve optimal quality of results and high manufacturing yield for Rapidus\u2019 2nm GAA process.\u201d<\/p>\n\n\n\n

By incorporating the concept of Manufacturing for Design (MFD) in addition to conventional Design for Manufacturing (DFM), Rapidus will be able to use sensors and AI in the wafer process to streamline designs based on silicon big data from the manufacturing process. This collaboration will incorporate Rapidus\u2019 big data into Synopsys AI-driven EDA flows to realize MFD for mutual customers. In addition, the Synopsys portfolio of interface and foundation IP for Rapidus process technologies will reduce integration risk and accelerate the path to silicon success.<\/p>\n\n\n\n

Rapidus is building its Rapid and Unified Manufacturing Service (RUMS) to shorten the overall time-to-market for customers by providing integrated design support and front-end and back-end processes that will continue to enhance design support through DMCO.<\/p>\n\n\n\n

Dr. Atsuyoshi Koike, CEO of Rapidus, said: \u201cOur partnership with Synopsys is an important milestone in helping to simplifying and quicken the design process. Rapidus\u2019 vision for RUMS is to use a single-wafer front-end process. The massive amount of data that can be obtained from this process is highly compatible with Synopsys AI-driven EDA flows and IP, and we believe that this will be a step toward achieving our goal of short TAT production that is quicker than anywhere else.\u201d<\/p>\n\n\n\n

About Rapidus Corporation<\/strong><\/h4>\n\n\n\n

Rapidus Corporation aims to develop and manufacture the world\u2019s most advanced logic semiconductors. By developing and providing services to shorten cycle times for design, wafer processes, 3D packaging, and other aspects of semiconductor production, Rapidus creates new industries together with customers. We continue to embrace challenges that contribute to the fulfillment, prosperity, and happiness of people\u2019s lives using semiconductors.<\/p>\n\n\n\n

\nAbout Rapidus Corporation
\nHeadquarters: 4-1 Kojimachi, Chiyoda-ku, Tokyo 102-0032, Japan
\nEstablishment: August 10th, 2022
\n
Executives: <\/span>\nTetsuro Higashi, Chairman of the Board of Directors
\nAtsuyoshi Koike, President and Representative Director\n<\/span>\n<\/div>\n
Business: <\/span>\nResearch, development, design, manufacture, and sales of semiconductor devices, integrated circuits and other electronic components<\/span>\n<\/div>\n\n
Capital, etc: <\/span>\n7,346 million yen (as of November 2022)
(includes the amount of capital reserve)<\/span>\n<\/div>\n<\/div>\n\n\n\n

U.S. Media Contact:<\/strong><\/p>\n\n\n\n

Devan Gillick \u2013 Breakaway Communications for Rapidus
Email: rapidus@breakawaycom.com<\/p>\n","protected":false},"featured_media":0,"parent":0,"menu_order":0,"template":"","news_cat":[9],"class_list":["post-1165","news_topics","type-news_topics","status-publish","hentry","news_cat-information","en-US"],"acf":[],"yoast_head":"\nRapidus Corporation<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2\/\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"11 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www-prenew.rapidus.inc\\\/en\\\/news_topics\\\/information\\\/rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2\\\/\",\"url\":\"https:\\\/\\\/www-prenew.rapidus.inc\\\/en\\\/news_topics\\\/information\\\/rapidus-collaborates-with-synopsys-to-shorten-semiconductor-design-cycles-2\\\/\",\"name\":\"Rapidus Collaborates with Synopsys to Shorten Semiconductor Design Cycles - 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