{"id":1162,"date":"2024-12-11T10:03:02","date_gmt":"2024-12-11T01:03:02","guid":{"rendered":"https:\/\/www.rapidus.inc\/wp\/?post_type=news_topics&p=1162"},"modified":"2024-12-11T10:05:07","modified_gmt":"2024-12-11T01:05:07","slug":"rapidus-collaborates-with-cadence-on-leading-edge-2nm","status":"publish","type":"news_topics","link":"https:\/\/www.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/","title":{"rendered":"Rapidus Collaborates with Cadence on Leading-Edge 2nm Semiconductor Solutions for AI and HPC ApplicationsCollaboration spans interface and memory IP utilizing 2nm gate-all-around, BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips<\/span>"},"content":{"rendered":"\n

Tokyo, SEMICON Japan Booth #2148, Dec. 10, 2024<\/strong>\u2014Rapidus Corporation<\/a>, a manufacturer of advanced logic semiconductors, today announced a collaboration with Cadence Design Systems, Inc.<\/a> to provide co-optimized AI-driven reference design flows and a broad IP portfolio. The new collaboration will support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from its backside power delivery network (BSPDN) technology to provide design solutions and IP portfolio to customers.<\/p>\n\n\n\n

As the semiconductor industry struggles to keep up with significantly increasing design challenges driven by the need for more computation, GAA and BSPDN manufacturing technologies are becoming vital to meet increasingly stringent power, performance and area requirements.<\/p>\n\n\n\n

Rapidus and Cadence are working to develop an AI-driven digital and analog\/mixed-signal reference design flow that includes Cadence design solutions. Customers will be able to use Cadence’s broad portfolio of interface and memory IP components, including HBM4, 224G SerDes, PCI Express 7.0 and more, while also taking advantage of 2nm GAA and BSPDN design and manufacturing solutions that support Rapidus’ Design for Manufacturing and Co-Optimization (DMCO) concept.<\/p>\n\n\n\n

\u201cOur broad collaboration with Rapidus for 2nm GAA BSPDN technology leverages Cadence\u2019s AI-driven solutions to solve real-world problems and meet customer needs,\u201d said Dr. Anirudh Devgan, president and CEO at Cadence. \u201cBy bringing together Cadence\u2019s advanced interface and memory IP technology, reference flows and Rapidus\u2019 process technology, we’re empowering the buildout of the AI infrastructure of tomorrow.\u201d<\/p>\n\n\n\n

\u201cOur collaboration with Cadence on 2nm BSPDN technology puts us at the industry\u2019s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we’re excited to set new technology standards and create transformative solutions for our mutual customers and the industry,\u201d said Dr. Atsuyoshi Koike, CEO of Rapidus.<\/p>\n\n\n\n

About Rapidus Corporation<\/strong><\/h4>\n\n\n\n

Rapidus Corporation aims to develop and manufacture the world’s most advanced logic semiconductors. We will create new industries together with our customers through the development and provision of services to shorten cycle times in design, wafer processes, 3D packaging, and more. We will continue to challenge ourselves in order to contribute to the fulfillment, prosperity, and happiness of people\u2019s lives through the use of semiconductors.<\/p>\n\n\n\n

\nAbout Rapidus Corporation
\nHeadquarters: 4-1 Kojimachi, Chiyoda-ku, Tokyo 102-0032, Japan
\nFounded: August 10, 2022
\n
Management: <\/span>\nTetsuro Higashi, Chairman of the Board of Directors
\nAtsuyoshi Koike, President and CEO\n<\/span>\n<\/div>\n
Business: <\/span>\nResearch, development, design, manufacture, and sales of semiconductor devices, integrated circuits and other electronic components<\/span>\n<\/div>\n\n
Capital, etc: <\/span>\n7,346 million yen (as of November 2022)
(includes the amount of capital reserve)<\/span>\n<\/div>\n<\/div>\n\n\n\n

U.S. Media Contact:<\/strong><\/p>\n\n\n\n

Devan Gillick \u2013 Breakaway Communications for Rapidus
Email: rapidus@breakawaycom.com<\/p>\n","protected":false},"featured_media":0,"parent":0,"menu_order":0,"template":"","news_cat":[9],"class_list":["post-1162","news_topics","type-news_topics","status-publish","hentry","news_cat-information","en-US"],"acf":[],"yoast_head":"\nRapidus Corporation<\/title>\n\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<meta property=\"og:type\" content=\"website\" \/>\n<meta property=\"og:site_name\" content=\"Rapidus Corporation\" \/>\n<meta property=\"og:title\" content=\"Rapidus Corporation\" \/>\n<meta property=\"og:description\" content=\"Tokyo, SEMICON Japan Booth #2148, Dec. 10, 2024\u2014Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced a collaboration with Cadence Design Systems, Inc. to provide co-optimized AI-driven reference design flows and a broad IP portfolio. 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The new collaboration will support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from […]","og_url":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/","og_locale":"en_US","twitter_card":"summary_large_image","canonical":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/","url":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/","name":"Rapidus Collaborates with Cadence on Leading-Edge 2nm Semiconductor Solutions for AI and HPC ApplicationsCollaboration spans interface and memory IP utilizing 2nm gate-all-around, BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips | Rapidus\u682a\u5f0f\u4f1a\u793e","isPartOf":{"@id":"https:\/\/www-prenew.rapidus.inc\/#website"},"datePublished":"2024-12-11T01:03:02+00:00","dateModified":"2024-12-11T01:05:07+00:00","breadcrumb":{"@id":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www-prenew.rapidus.inc\/en\/news_topics\/information\/rapidus-collaborates-with-cadence-on-leading-edge-2nm\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"\u30db\u30fc\u30e0","item":"https:\/\/www-prenew.rapidus.inc\/"},{"@type":"ListItem","position":2,"name":"NEWS","item":"https:\/\/www-prenew.rapidus.inc\/news_topics\/"},{"@type":"ListItem","position":3,"name":"Rapidus Collaborates with Cadence on Leading-Edge 2nm Semiconductor Solutions for AI and HPC ApplicationsCollaboration spans interface and memory IP utilizing 2nm gate-all-around, BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips"}]},{"@type":"WebSite","@id":"https:\/\/www-prenew.rapidus.inc\/#website","url":"https:\/\/www-prenew.rapidus.inc\/","name":"Rapidus\u682a\u5f0f\u4f1a\u793e","description":"","publisher":{"@id":"https:\/\/www-prenew.rapidus.inc\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www-prenew.rapidus.inc\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/www-prenew.rapidus.inc\/#organization","name":"Rapidus\u682a\u5f0f\u4f1a\u793e","url":"https:\/\/www-prenew.rapidus.inc\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www-prenew.rapidus.inc\/#\/schema\/logo\/image\/","url":"https:\/\/www.rapidus.inc\/wp\/wp-content\/uploads\/2024\/12\/favicon.png","contentUrl":"https:\/\/www.rapidus.inc\/wp\/wp-content\/uploads\/2024\/12\/favicon.png","width":512,"height":512,"caption":"Rapidus\u682a\u5f0f\u4f1a\u793e"},"image":{"@id":"https:\/\/www-prenew.rapidus.inc\/#\/schema\/logo\/image\/"}}]}},"_links":{"self":[{"href":"https:\/\/www.rapidus.inc\/wp-json\/wp\/v2\/news_topics\/1162","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.rapidus.inc\/wp-json\/wp\/v2\/news_topics"}],"about":[{"href":"https:\/\/www.rapidus.inc\/wp-json\/wp\/v2\/types\/news_topics"}],"wp:attachment":[{"href":"https:\/\/www.rapidus.inc\/wp-json\/wp\/v2\/media?parent=1162"}],"wp:term":[{"taxonomy":"news_cat","embeddable":true,"href":"https:\/\/www.rapidus.inc\/wp-json\/wp\/v2\/news_cat?post=1162"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}